Information

5.7.2 WDOG clocking
The WDOG may be clocked from two clock sources as shown in the following figure.
WDOG_STCTRLH[CLKSRC]
WDOG clock
Bus clock
LPO
Figure 5-2. WDOG clock generation
5.7.3 Debug trace clock
The debug trace clock source can be clocked as shown in the following figure.
SIM_SOPT2[TRACECLKSEL]
TRACECLKIN
Core / system clock
MCGOUTCLK
TPIU
÷2
TRACE_CLKOUT
Figure 5-3. Trace clock generation
NOTE
The trace clock frequency observed at the TRACE_CLKOUT
pin will be half that of the selected clock source.
5.7.4 PORT digital filter clocking
The digital filters in each of the PORTx modules can be clocked as shown in the
following figure.
Chapter 5 Clock Distribution
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 171