Information

NOTE
In stop mode, the digital input filters are bypassed unless they
are configured to run from the 1 kHz LPO clock source.
PORTx_DFCR[CS]
PORTx digital input
filter clock
Bus clock
LPO
Figure 5-4. PORTx digital input filter clock generation
5.7.5 LPTMR clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown
in the following figure.
NOTE
The chosen clock must remain enabled if the LPTMRx is to
continue operating in all required low-power modes.
LPTMRx_PSR[PCS]
LPTMRx prescaler/glitch
filter clock
MCGIRCLK
OSCERCLK
ERCLK32K
LPO
Figure 5-5. LPTMRx prescaler/glitch filter clock generation
5.7.6 FlexCAN clocking
The clock for the FlexCAN's protocol engine can be selected as shown in the following
figure.
Module clocks
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
172 Freescale Semiconductor, Inc.