Information

CANx_CTRL1[CLKSRC]
FlexCAN clock
Bus clock
OSCERCLK
Figure 5-6. FlexCAN clock generation
5.7.7 UART clocking
UART0 and UART1 modules operate from the core/system clock, which provides higher
performance level for these modules. All other UART modules operate from the bus
clock.
5.7.8 SDHC clocking
The SDHC module has four possible clock sources for the external clock source, as
shown in the following figure.
SIM_SOPT2[SDHCSRC]
SDHC clock
MCGPLLCLK or
MCGFLLCLK
Core / system clock
OSCERCLK
SDHC0_CLKIN
Figure 5-7. SDHC clock generation
Chapter 5 Clock Distribution
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 173