Information

5.7.9 I
2
S clocking
In addition to the bus clock, the I
2
S has a clock source for master clock generation. The
maximum frequency of this clock is 50 MHz. The master clock source can be derived
from several sources, as shown in the following figure.
SIM_SOPT2[I2SSRC]
Core/system clock
MCGPLLCLK or
MCGFLLCLK
OSCERCLK
S master clockI
2
I2S_CLKIN
SIM_CLKDIV2
[I2SFRAC,I2SDIV]
Figure 5-8. I
2
S baud clock generation
5.7.10 TSI clocking
In active mode, the TSI can be clocked as shown in the following figure.
TSI_SCANC[AMCLKS]
TSI clock
in active mode
Bus clock
MCGIRCLK
OSCERCLK
Figure 5-9. TSI clock generation
In low-power mode, the TSI can be clocked as shown in the following figure.
NOTE
In the TSI chapter, these two clocks are referred to as LPOCLK
and VLPOSCCLK.
Module clocks
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
174 Freescale Semiconductor, Inc.