Information

Table 7-2. Module operation in low power modes (continued)
Modules Stop VLPR VLPW VLPS LLS VLLSx
FlexMemory
3
low power low power
4
low power low power low power low power in
VLLS3, OFF in
VLLS2 and
VLLS1
Register files
5
powered powered powered powered powered powered
FlexBus static FF FF static static OFF
EzPort disabled disabled disabled disabled disabled disabled
Communication interfaces
UART static, wakeup
on edge
125 kbps 125 kbps static, wakeup
on edge
static OFF
SPI static 1 Mbps 1 Mbps static static OFF
I
2
C static, address
match wakeup
100 kbps 100 kbps static, address
match wakeup
static OFF
CAN wakeup 256 kbps 256 kbps wakeup static OFF
I
2
S FF with external
clock
6
FF FF FF with external
clock
6
static OFF
SDHC wakeup FF FF wakeup static OFF
Security
CRC static FF FF static static OFF
Timers
FTM static FF FF static static OFF
PIT static FF FF static static OFF
PDB static FF FF static static OFF
LPTMR FF FF FF FF FF FF
RTC - 32kHz
OSC
5
FF FF FF FF FF FF
CMT static FF FF static static OFF
Analog
16-bit ADC ADC internal
clock only
FF FF ADC internal
clock only
static OFF
CMP
7
HS or LS
compare
FF FF HS or LS
compare
LS compare LS compare
6-bit DAC static FF FF static static static
VREF FF FF FF FF static OFF
12-bit DAC static FF FF static static static
Human-machine interfaces
GPIO wakeup FF FF wakeup static, pins
latched
OFF, pins
latched
TSI wakeup FF FF wakeup wakeup
8
wakeup
8
Chapter 7 Power Management
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 193