Information

It is important to note that these DAP control and status registers are not memory mapped
within the system memory map and are only accessible via the Debug Access Port (DAP)
using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with
the available registers shown in the table below.
Table 9-4. MDM-AP Register Summary
Address Register Description
0x0100_0000 Status See MDM-AP Status Register
0x0100_0004 Control See MDM-AP Control Register
0x0100_00FC ID Read-only identification register that
always reads as 0x001C_0000
SWJ-DP
SELECT[31:24] (APSEL) selects the AP
SELECT[7:4] (APBANKSEL) selects the bank
A[3:2] from the APACC selects the register
within the bank
AHB Access Port
(AHB-AP)
MDM-AP
Status
0x00
Control
0x01
IDR
0x3F
AHB-AP
SELECT[31:24] = 0x00 selects the AHB-AP
See ARM documentation for further details
MDM-AP
SELECT[31:24] = 0x01 selects the MDM-AP
SELECT[7:4] = 0x0 selects the bank with Status and Ctrl
A[3:2] = 2’b00 selects the Status Register
A[3:2] = 2’b01 selects the Control Register
SELECT[7:4] = 0xF selects the bank with IDR
A[3:2] = 2’b11 selects the IDR Register
(IDR register reads 0x001C_0000)
Bus Matrix
See Control and Status Register
Descriptions
Debug PortInternal BusAccess Port
Data[31:0] A[7:4] A[3:2] RnW
APSEL
Decode
Debug Port ID Register (DPIDR)
Control/Status (CTRL/STAT)
AP Select (SELECT)
Read Buffer (REBUFF)
DP Registers
0x00
0x04 0x08 0x0C
Data[31:0] A[3:2] RnW
DPACC
Data[31:0] A[3:2] RnW
APACC
Debug Port
(DP)
Generic
See the ARM Debug Interface v5p1 Supplement.
Figure 9-3. MDM AP Addressing
Chapter 9 Debug
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 205