Information

10.3.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
LQF
P
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
— L5 RESERVED RESERVED RESERVED
— M5 NC NC NC
— A10 NC NC NC
— B10 NC NC NC
— C10 NC NC NC
1 D3 PTE0 ADC1_SE4
a
ADC1_SE4
a
PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA
2 D2 PTE1/
LLWU_P0
ADC1_SE5
a
ADC1_SE5
a
PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL
3 D1 PTE2/
LLWU_P1
ADC1_SE6
a
ADC1_SE6
a
PTE2/
LLWU_P1
SPI1_SCK UART1_CT
S_b
SDHC0_DC
LK
4 E4 PTE3 ADC1_SE7
a
ADC1_SE7
a
PTE3 SPI1_SIN UART1_RT
S_b
SDHC0_CM
D
5 E5 VDD VDD VDD
6 F6 VSS VSS VSS
7 E3 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2
9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CT
S_b
I2S0_MCLK I2S0_CLKIN
10 F4 PTE7 DISABLED PTE7 UART3_RT
S_b
I2S0_RXD
11 F3 PTE8 DISABLED PTE8 UART5_TX I2S0_RX_F
S
12 F2 PTE9 DISABLED PTE9 UART5_RX I2S0_RX_B
CLK
13 F1 PTE10 DISABLED PTE10 UART5_CT
S_b
I2S0_TXD
14 G4 PTE11 DISABLED PTE11 UART5_RT
S_b
I2S0_TX_F
S
15 G3 PTE12 DISABLED PTE12 I2S0_TX_B
CLK
16 E6 VDD VDD VDD
17 F7 VSS VSS VSS
18 H1 PTE16 ADC0_SE4
a
ADC0_SE4
a
PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN
0
FTM0_FLT3
Chapter 10 Signal Multiplexing and Signal Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 217