Information

144
LQF
P
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
19 H2 PTE17 ADC0_SE5
a
ADC0_SE5
a
PTE17 SPI0_SCK UART2_RX FTM_CLKIN
1
LPT0_ALT3
20 G1 PTE18 ADC0_SE6
a
ADC0_SE6
a
PTE18 SPI0_SOUT UART2_CT
S_b
I2C0_SDA
21 G2 PTE19 ADC0_SE7
a
ADC0_SE7
a
PTE19 SPI0_SIN UART2_RT
S_b
I2C0_SCL
22 H3 VSS VSS VSS
23 J1 ADC0_DP1 ADC0_DP1 ADC0_DP1
24 J2 ADC0_DM1 ADC0_DM1 ADC0_DM1
25 K1 ADC1_DP1 ADC1_DP1 ADC1_DP1
26 K2 ADC1_DM1 ADC1_DM1 ADC1_DM1
27 L1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
28 L2 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
29 M1 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
30 M2 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
31 H5 VDDA VDDA VDDA
32 G5 VREFH VREFH VREFH
33 G6 VREFL VREFL VREFL
34 H6 VSSA VSSA VSSA
35 K3 ADC1_SE1
6/
CMP2_IN2/
ADC0_SE2
2
ADC1_SE1
6/
CMP2_IN2/
ADC0_SE2
2
ADC1_SE1
6/
CMP2_IN2/
ADC0_SE2
2
36 J3 ADC0_SE1
6/
CMP1_IN2/
ADC0_SE2
1
ADC0_SE1
6/
CMP1_IN2/
ADC0_SE2
1
ADC0_SE1
6/
CMP1_IN2/
ADC0_SE2
1
37 M3 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
38 L3 DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
39 L4 DAC1_OUT/
CMP2_IN3/
DAC1_OUT/
CMP2_IN3/
DAC1_OUT/
CMP2_IN3/
Pinout
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
218 Freescale Semiconductor, Inc.