Information

144
LQF
P
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
ADC1_SE2
3
ADC1_SE2
3
ADC1_SE2
3
40 M7 XTAL32 XTAL32 XTAL32
41 M6 EXTAL32 EXTAL32 EXTAL32
42 L6 VBAT VBAT VBAT
43 — VDD VDD VDD
44 — VSS VSS VSS
45 M4 PTE24 ADC0_SE1
7
ADC0_SE1
7
PTE24 CAN1_TX UART4_TX EWM_OUT
_b
46 K5 PTE25 ADC0_SE1
8
ADC0_SE1
8
PTE25 CAN1_RX UART4_RX EWM_IN
47 K4 PTE26 DISABLED PTE26 UART4_CT
S_b
RTC_CLKO
UT
48 J4 PTE27 DISABLED PTE27 UART4_RT
S_b
49 H4 PTE28 DISABLED PTE28
50 J5 PTA0 JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CT
S_b
FTM0_CH5 JTAG_TCL
K/
SWD_CLK
EZP_CLK
51 J6 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
52 K6 PTA2 JTAG_TDO/
TRACE_SW
O/EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SW
O
EZP_DO
53 K7 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RT
S_b
FTM0_CH0 JTAG_TMS/
SWD_DIO
54 L7 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
55 M8 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_B
CLK
JTAG_TRS
T
56 E7 VDD VDD VDD
57 G7 VSS VSS VSS
58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_CL
KOUT
59 J8 PTA7 ADC0_SE1
0
ADC0_SE1
0
PTA7 FTM0_CH4 TRACE_D3
60 K8 PTA8 ADC0_SE1
1
ADC0_SE1
1
PTA8 FTM1_CH0 FTM1_QD_
PHA
TRACE_D2
61 L8 PTA9 DISABLED PTA9 FTM1_CH1 FTM1_QD_
PHB
TRACE_D1
62 M9 PTA10 DISABLED PTA10 FTM2_CH0 FTM2_QD_
PHA
TRACE_D0
63 L9 PTA11 DISABLED PTA11 FTM2_CH1 FTM2_QD_
PHB
64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_
PHA
Chapter 10 Signal Multiplexing and Signal Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 219