Information

144
LQF
P
144
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
88 F11 PTB7 /
ADC1_SE1
3
/
ADC1_SE1
3
PTB7 FB_AD22
89 F10 PTB8 PTB8 UART3_RT
S_b
FB_AD21
90 F9 PTB9 PTB9 SPI1_PCS1 UART3_CT
S_b
FB_AD20
91 E12 PTB10 /
ADC1_SE1
4
/
ADC1_SE1
4
PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1
92 E11 PTB11 /
ADC1_SE1
5
/
ADC1_SE1
5
PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2
93 H7 VSS VSS VSS
94 F5 VDD VDD VDD
95 E10 PTB16 /TSI0_CH9 /TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN
96 E9 PTB17 /TSI0_CH10 /TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT
_b
97 D12 PTB18 /TSI0_CH11 /TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_B
CLK
FB_AD15 FTM2_QD_
PHA
98 D11 PTB19 /TSI0_CH12 /TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_F
S
FB_OE_b FTM2_QD_
PHB
99 D10 PTB20 PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT
100 D9 PTB21 PTB21 SPI2_SCK FB_AD30 CMP1_OUT
101 C12 PTB22 PTB22 SPI2_SOUT FB_AD29 CMP2_OUT
102 C11 PTB23 PTB23 SPI2_SIN SPI0_PCS5 FB_AD28
103 B12 PTC0 /
ADC0_SE1
4/
TSI0_CH13
/
ADC0_SE1
4/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXT
RG
I2S0_TXD FB_AD14
104 B11 PTC1/
LLWU_P6
/
ADC0_SE1
5/
TSI0_CH14
/
ADC0_SE1
5/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RT
S_b
FTM0_CH0 FB_AD13
105 A12 PTC2 /
ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
/
ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CT
S_b
FTM0_CH1 FB_AD12
106 A11 PTC3/
LLWU_P7
/CMP1_IN1 /CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 FB_CLKOU
T
107 H8 VSS VSS VSS
108 — VDD VDD VDD
109 A9 PTC4/
LLWU_P8
PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT
110 D8 PTC5/
LLWU_P9
PTC5/
LLWU_P9
SPI0_SCK LPT0_ALT2 FB_AD10 CMP0_OUT
Chapter 10 Signal Multiplexing and Signal Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 221