Information

Table 10-10. FlexBus Signal Descriptions
Chip signal name Module signal
name
Description I/O
FB_CLKOUT FB_CLK FlexBus clock output O
FB_A[29:16] FB_A[29:16] In a non-multiplexed configuration, this is the address bus. O
FB_AD[31:0] FB_D[31:0]/
FB_AD[31:0]
In a non-multiplexed configuration, this is the data bus. In a
multiplexed configuration this bus is the address/data bus,
FB_AD[31:0]. In non-multiplexed and multiplexed configurations,
during the first cycle, this bus drives the upper address byte,
addr[31:24].
I/O
FB_CS[5:0] FB_CS[5:0] General purpose chip-selects. The actual number of chip selects
available depends upon the device and its pin configuration.
O
FB_BE31_24_BLS7
_0,
FB_BE23_16_BLS1
5_8,
FB_BE15_8_BLS23
_16,
FB_BE7_0_BLS31_
24
FB_BE_31_24
FB_BE_23_16
FB_BE_15_8
FB_BE_7_0
Byte enables O
FB_OE FB_OE Output enable O
FB_R W FB_R/W Read/write. 1 = Read, 0 = Write O
FB_TS/ FB_ALE FB_TS Transfer start O
FB_TSIZ[1:0] FB_TSIZ[1:0] Transfer size O
FB_TA FB_TA Transfer acknowledge I
FB_TBST FB_TBST Burst transfer indicator O
10.4.5 Analog
Table 10-11. ADC 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
ADC0_DP3,
PGA0_DP,
ADC0_DP[1:0]
DADP[3:0] Differential analog channel inputs I
ADC0_DM3,
PGA0_DM,
ADC0_DM[1:0]
DADM[3:0] Differential analog channel inputs I
ADC0_SE[18:4] AD[23:4] Single-ended analog channel inputs I
VREFH V
REFSH
Voltage reference select high I
VREFL V
REFSL
Voltage reference select low I
VDDA V
DDA
Analog power supply I
Table continues on the next page...
Module Signal Description Tables
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
228 Freescale Semiconductor, Inc.