Information

Table 10-11. ADC 0 Signal Descriptions (continued)
Chip signal name Module signal
name
Description I/O
VSSA V
SSA
Analog ground I
Table 10-12. ADC 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
ADC1_DP3,
PGA1_DP,
ADC1_DP[1:0]
DADP[3:0] Differential analog channel inputs I
ADC1_DM3,
PGA1_DM,
ADC1_DM[1:0]
DADM[3:0] Differential analog channel inputs I
ADC1_SE[18:4] AD[23:4] Single-ended analog channel inputs I
VREFH V
REFSH
Voltage reference select high I
VREFL V
REFSL
Voltage reference select low I
VDDA V
DDA
Analog power supply I
VSSA V
SSA
Analog ground I
Table 10-13. CMP 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP0_IN[5:0] IN[5:0] Analog voltage inputs I
CMP0_OUT CMPO Comparator output O
Table 10-14. CMP 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP1_IN[5:0] IN[5:0] Analog voltage inputs I
CMP1_OUT CMPO Comparator output O
Table 10-15. CMP 2 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP2_IN[5:0] IN[5:0] Analog voltage inputs I
CMP2_OUT CMPO Comparator output O
Chapter 10 Signal Multiplexing and Signal Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 229