Information

• Selectable clock source for digital input filter with 5-bit resolution on filter size
• Digital filter is functional in all digital pin muxing modes
• Port control
• Individual pull control registers with pullup, pulldown and pull-disable support
• Individual drive strength register supporting high and low drive strength
• Individual slew rate register supporting fast and slow slew rates
• Individual input passive filter register supporting enabled and disabled
• Individual open-drain register supporting enabled and disabled
• Individual mux control register supporting analog (or pin disabled), GPIO plus
up to six chip specific digital functions
• Pad configuration registers are functional in all digital pin muxing modes
11.1.3 Modes of operation
11.1.3.1 Run mode
In run mode, the PORT operates normally.
11.1.3.2 Wait mode
In wait mode, the PORT continues to operate normally and may be configured to exit the
low power mode if an enabled interrupt is detected. DMA requests are still generated
during wait mode, but do not cause an exit from the low power mode.
11.1.3.3 Stop mode
In stop mode, the digital input filters are bypassed unless they are configured to run from
the 1 kHz LPO clock source. The PORT can be configured to exit the low power mode
via an asynchronous wakeup signal if an enabled interrupt (but not DMA request) is
detected.
11.1.3.4 Debug mode
In debug mode, the PORTx operates normally.
Introduction
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
236 Freescale Semiconductor, Inc.