Information

11.2 External signal description
Table 11-1. Signal properties
Name Function I/O Reset Pull
PORTx[31:0] External interrupt I/O 0 -
NOTE
Not all pins within each port are implemented on each device.
11.3 Detailed signal descriptions
Table 11-2. PORTx interface-detailed signal descriptions
Signal I/O Description
PORTx[31:0] I/O External interrupt.
State meaning Asserted-pin is logic one.
Negated-pin is logic zero.
Timing Assertion-may occur at any
time and can assert
asynchronously to the system
clock.
Negation-may occur at any
time and can assert
asynchronously to the system
clock.
11.4 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W 0000_0000h 11.4.1/244
4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W 0000_0000h 11.4.1/244
4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W 0000_0000h 11.4.1/244
Table continues on the next page...
Chapter 11 Port control and interrupts (PORT)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 237