Information
PORTx_PCRn field descriptions (continued)
Field Description
1001 Interrupt on rising edge.
1010 Interrupt on falling edge.
1011 Interrupt on either edge.
1100 Interrupt when logic one.
Others Reserved.
15
LK
Lock Register
0 Pin Control Register bits [15:0] are not locked.
1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
14–11
Reserved
This read-only field is reserved and always has the value zero.
10–8
MUX
Pin Mux Control
The corresponding pin is configured as follows:
000 Pin Disabled (Analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip specific).
011 Alternative 3 (chip specific).
100 Alternative 4 (chip specific).
101 Alternative 5 (chip specific).
110 Alternative 6 (chip specific).
111 Alternative 7 (chip specific / JTAG / NMI).
7
Reserved
This read-only field is reserved and always has the value zero.
6
DSE
Drive Strength Enable
Drive Strength configuration is valid in all digital pin muxing modes.
0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
5
ODE
Open Drain Enable
Open Drain configuration is valid in all digital pin muxing modes.
0 Open Drain output is disabled on the corresponding pin.
1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
4
PFE
Passive Filter Enable
Passive Filter configuration is valid in all digital pin muxing modes.
0 Passive Input Filter is disabled on the corresponding pin.
1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input.
A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the
Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
3
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 11 Port control and interrupts (PORT)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 245