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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 144 (13x13) 32-Bit 100 MHz I/O number 104
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PORTx_PCRn field descriptions (continued)
Field Description
2
SRE
Slew Rate Enable
Slew Rate configuration is valid in all digital pin muxing modes.
0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
1
PE
Pull Enable
Pull configuration is valid in all digital pin muxing modes.
0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured
as a digital input.
0
PS
Pull Select
Pull configuration is valid in all digital pin muxing modes.
0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable
Register bit is set.
1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable
Register bit is set.
11.4.2 Global Pin Control Low Register (PORTx_GPCLR)
Addresses: PORTA_GPCLR is 4004_9000h base + 80h offset = 4004_9080h
PORTB_GPCLR is 4004_A000h base + 80h offset = 4004_A080h
PORTC_GPCLR is 4004_B000h base + 80h offset = 4004_B080h
PORTD_GPCLR is 4004_C000h base + 80h offset = 4004_C080h
PORTE_GPCLR is 4004_D000h base + 80h offset = 4004_D080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
GPWE GPWD
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_GPCLR field descriptions
Field Description
31–16
GPWE
Global Pin Write Enable
When set, causes bits [15:0] of the corresponding Pin Control Register (15 through 0) to update with the
value in the Global Pin Write Data field.
15–0
GPWD
Global Pin Write Data
Value to be written to bits [15:0] of all Pin Control Registers that are enabled by the Global Pin Write
Enable field, provided the corresponding register has not been locked.
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
246 Freescale Semiconductor, Inc.