Information

11.4.6 Digital Filter Clock Register (PORTx_DFCR)
Addresses: PORTA_DFCR is 4004_9000h base + C4h offset = 4004_90C4h
PORTB_DFCR is 4004_A000h base + C4h offset = 4004_A0C4h
PORTC_DFCR is 4004_B000h base + C4h offset = 4004_B0C4h
PORTD_DFCR is 4004_C000h base + C4h offset = 4004_C0C4h
PORTE_DFCR is 4004_D000h base + C4h offset = 4004_D0C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_DFCR field descriptions
Field Description
31–1
Reserved
This read-only field is reserved and always has the value zero.
0
CS
Clock Source
The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the
digital input filters. Changing the filter clock source should only be done after disabling all enabled digital
filters.
0 Digital Filters are clocked by the bus clock.
1 Digital Filters are clocked by the 1 kHz LPO clock.
11.4.7 Digital Filter Width Register (PORTx_DFWR)
The digital filter configuration is valid in all digital pin muxing modes.
Addresses: PORTA_DFWR is 4004_9000h base + C8h offset = 4004_90C8h
PORTB_DFWR is 4004_A000h base + C8h offset = 4004_A0C8h
PORTC_DFWR is 4004_B000h base + C8h offset = 4004_B0C8h
PORTD_DFWR is 4004_C000h base + C8h offset = 4004_C0C8h
PORTE_DFWR is 4004_D000h base + C8h offset = 4004_D0C8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FILT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 11 Port control and interrupts (PORT)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 249