Information

12.1.3 SIM Signal Descriptions
Table 12-1. SIM Signal Descriptions
Signa
l
Description I/O
EZP_
CS
EzPort mode select I
12.1.3.1 Detailed signal description
Table 12-2. SIM interface-detailed signal descriptions
Signal I/O Description
EZP_CS I EZPORT mode select
State meaning Assertion-0 - Configure part for EZPORT
mode
Negation- 1 - Configure part for normal flash
operation
Timing As a mode select, this signal is only
recognized during reset although it can be
asserted and negated at any time.
Assertion-May occur at any time; input may
be asserted asynchronously to the system
clock.
Negation-May occur at any time; input may
be negated asynchronously to the system
clock.
12.2 Memory map and register definition
The SIM module contains many bitfields for selecting the clock source and dividers for
various module clocks. See the Clock Distribution chapter for more information
including block diagrams and clock definitions.
NOTE
The SIM_SOPT1 register is located at a different base address
than the other SIM registers.
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
254 Freescale Semiconductor, Inc.