Information

12.2.2 System Options Register 2 (SIM_SOPT2)
SOPT2 contains the controls for selecting many of the module clock source options on
this device. See the Clock Distribution chapter for more information including clocking
diagrams and definitions of device clocks.
Address: SIM_SOPT2 is 4004_7000h base + 1004h offset = 4004_8004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SDHCSRC
0
I2SSRC
0 0 0 0 0
PLLFLLSEL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRACECLKSEL
CMTUARTPAD
0
FBSL
0
MCGCLKSEL
W
Reset
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
SIM_SOPT2 field descriptions
Field Description
31–30
Reserved
This read-only field is reserved and always has the value zero.
29–28
SDHCSRC
SDHC clock source select
Selects the clock source for the SDHC clock.
00 Core/system clock.
01 MCGPLLCLK/MCGFLLCLK clock
10 OSCERCLK clock
11 External bypass clock (SDHC0_CLKIN)
27–26
Reserved
This read-only field is reserved and always has the value zero.
25–24
I2SSRC
I2S master clock source select
Selects the clock source for I
2
S master clock.
00 Core/system clock divided by the I
2
S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC,
I2SDIV] descriptions.
01 MCGPLLCLK/MCGFLLCLK clock divided by the I
2
S fractional clock divider. See the
SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions.
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
258 Freescale Semiconductor, Inc.