Information

SIM_SCGC1 field descriptions (continued)
Field Description
11
UART5
UART5 Clock Gate Control
This bit controls the clock gate to the UART5 module.
0 Clock disabled
1 Clock enabled
10
UART4
UART4 Clock Gate Control
This bit controls the clock gate to the UART4 module.
0 Clock disabled
1 Clock enabled
9–0
Reserved
This read-only field is reserved and always has the value zero.
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)
Address: SIM_SCGC2 is 4004_7000h base + 102Ch offset = 4004_802Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DAC1 DAC0
0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_SCGC2 field descriptions
Field Description
31–14
Reserved
This read-only field is reserved and always has the value zero.
13
DAC1
DAC1 Clock Gate Control
This bit controls the clock gate to the DAC1 module.
0 Clock disabled
1 Clock enabled
12
DAC0
DAC0 Clock Gate Control
This bit controls the clock gate to the DAC0 module.
0 Clock disabled
1 Clock enabled
11–1
Reserved
This read-only field is reserved and always has the value zero.
0
Reserved
This read-only field is reserved and always has the value zero.
Chapter 12 System integration module (SIM)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 269