Information

SIM_SCGC4 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
27–21
Reserved
This read-only field is reserved and always has the value zero.
20
VREF
VREF Clock Gate Control
This bit controls the clock gate to the VREF module.
0 Clock disabled
1 Clock enabled
19
CMP
Comparator Clock Gate Control
This bit controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
18
Reserved
This read-only field is reserved and always has the value zero.
17–14
Reserved
This read-only field is reserved and always has the value zero.
13
UART3
UART3 Clock Gate Control
This bit controls the clock gate to the UART3 module.
0 Clock disabled
1 Clock enabled
12
UART2
UART2 Clock Gate Control
This bit controls the clock gate to the UART2 module.
0 Clock disabled
1 Clock enabled
11
UART1
UART1 Clock Gate Control
This bit controls the clock gate to the UART1 module.
0 Clock disabled
1 Clock enabled
10
UART0
UART0 Clock Gate Control
This bit controls the clock gate to the UART0 module.
0 Clock disabled
1 Clock enabled
9–8
Reserved
This read-only field is reserved and always has the value zero.
7
I2C1
I2C1 Clock Gate Control
This bit controls the clock gate to the I
2
C1 module.
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
272 Freescale Semiconductor, Inc.