Information

SIM_SCGC4 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
6
I2C0
I2C0 Clock Gate Control
This bit controls the clock gate to the I
2
C0 module.
0 Clock disabled
1 Clock enabled
5–4
Reserved
This read-only field is reserved and always has the value one.
3
Reserved
This read-only field is reserved and always has the value zero.
2
CMT
CMT Clock Gate Control
This bit controls the clock gate to the CMT module.
0 Clock disabled
1 Clock enabled
1
EWM
EWM Clock Gate Control
This bit controls the clock gate to the EWM module.
0 Clock disabled
1 Clock enabled
0
Reserved
This read-only field is reserved and always has the value zero.
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)
Address: SIM_SCGC5 is 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 1 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PORTE
PORTD PORTC
PORTB PORTA
1 0
TSI
0
REGFILE
LPTIMER
W
Reset
0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0
Chapter 12 System integration module (SIM)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 273