Information

SIM_SCGC5 field descriptions
Field Description
31–19
Reserved
This read-only field is reserved and always has the value zero.
18
Reserved
This read-only field is reserved and always has the value one.
17–14
Reserved
This read-only field is reserved and always has the value zero.
13
PORTE
Port E Clock Gate Control
This bit controls the clock gate to the Port E module.
0 Clock disabled
1 Clock enabled
12
PORTD
Port D Clock Gate Control
This bit controls the clock gate to the Port D module.
0 Clock disabled
1 Clock enabled
11
PORTC
Port C Clock Gate Control
This bit controls the clock gate to the Port C module.
0 Clock disabled
1 Clock enabled
10
PORTB
Port B Clock Gate Control
This bit controls the clock gate to the Port B module.
0 Clock disabled
1 Clock enabled
9
PORTA
Port A Clock Gate Control
This bit controls the clock gate to the Port A module.
0 Clock disabled
1 Clock enabled
8–7
Reserved
This read-only field is reserved and always has the value one.
6
Reserved
This read-only field is reserved and always has the value zero.
5
TSI
TSI Clock Gate Control
This bit controls the clock gate to the TSI module.
0 Clock disabled
1 Clock enabled
4–2
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
274 Freescale Semiconductor, Inc.