Information

SIM_SCGC6 field descriptions (continued)
Field Description
28
Reserved
This read-only field is reserved and always has the value zero.
27
ADC0
ADC0 Clock Gate Control
This bit controls the clock gate to the ADC0 module.
0 Clock disabled
1 Clock enabled
26
Reserved
This read-only field is reserved and always has the value zero.
25
FTM1
FTM1 Clock Gate Control
This bit controls the clock gate to the FTM1 module.
0 Clock disabled
1 Clock enabled
24
FTM0
FTM0 Clock Gate Control
This bit controls the clock gate to the FTM0 module.
0 Clock disabled
1 Clock enabled
23
PIT
PIT Clock Gate Control
This bit controls the clock gate to the PIT module.
0 Clock disabled
1 Clock enabled
22
PDB
PDB Clock Gate Control
This bit controls the clock gate to the PDB module.
0 Clock disabled
1 Clock enabled
21
Reserved
This read-only field is reserved and always has the value zero.
20–19
Reserved
This read-only field is reserved and always has the value zero.
18
CRC
CRC Clock Gate Control
This bit controls the clock gate to the CRC module.
0 Clock disabled
1 Clock enabled
17–16
Reserved
This read-only field is reserved and always has the value zero.
15
I2S
I2S Clock Gate Control
This bit controls the clock gate to the I
2
S module.
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
276 Freescale Semiconductor, Inc.