Information

Section Number Title Page
34.5.4 Low Power Mode Operation........................................................................................................................844
Chapter 35
Voltage Reference (VREFV1)
35.1 Introduction...................................................................................................................................................................847
35.1.1 Overview......................................................................................................................................................848
35.1.2 Features........................................................................................................................................................848
35.1.3 Modes of Operation.....................................................................................................................................849
35.1.4 VREF Signal Descriptions...........................................................................................................................849
35.2 Memory Map and Register Definition..........................................................................................................................849
35.2.1 VREF Trim Register (VREF_TRM)............................................................................................................850
35.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................851
35.3 Functional Description..................................................................................................................................................852
35.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................852
35.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................852
35.4 Initialization/Application Information..........................................................................................................................853
Chapter 36
Programmable Delay Block (PDB)
36.1 Introduction...................................................................................................................................................................855
36.1.1 Features........................................................................................................................................................855
36.1.2 Implementation............................................................................................................................................856
36.1.3 Back-to-back Acknowledgement Connections............................................................................................857
36.1.4 DAC External Trigger Input Connections...................................................................................................857
36.1.5 Block Diagram.............................................................................................................................................857
36.1.6 Modes of Operation.....................................................................................................................................859
36.2 PDB Signal Descriptions..............................................................................................................................................859
36.3 Memory Map and Register Definition..........................................................................................................................859
36.3.1 Status and Control Register (PDBx_SC).....................................................................................................861
36.3.2 Modulus Register (PDBx_MOD).................................................................................................................863
36.3.3 Counter Register (PDBx_CNT)...................................................................................................................864
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
30 Freescale Semiconductor, Inc.