Information

MC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_E000 System Reset Status Register High (MC_SRSH) 8 R/W 00h 13.2.1/304
4007_E001 System Reset Status Register Low (MC_SRSL) 8 R/W 82h 13.2.2/305
4007_E002 Power Mode Protection Register (MC_PMPROT) 8 R/W 00h 13.2.3/306
4007_E003 Power Mode Control Register (MC_PMCTRL) 8 R/W 00h 13.2.4/308
13.2.1 System Reset Status Register High (MC_SRSH)
The SRSH:SRSL registers include read-only status flags to indicate the source of the
most recent reset. The reset state of these bits depends on what caused the MCU to reset.
Throughout this document, SRS refers to SRSH:SRSL.
NOTE
The reset value of this register depends on the reset type:
• POR — 0x00
• LVD — 0x00
• Low-leakage wake-up (LLS exit via RESET pin or any exit
from VLLS) — 0x00
• Other reset — bits 2-0 are set if their corresponding reset
source caused the reset
Address: MC_SRSH is 4007_E000h base + 0h offset = 4007_E000h
Bit 7 6 5 4 3 2 1 0
Read 0 SW LOCKUP JTAG
Write
Reset
0 0 0 0 0 0 0 0
MC_SRSH field descriptions
Field Description
7–3
Reserved
This read-only field is reserved and always has the value zero.
2
SW
Software
Indicates reset was caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset
Control Register in the ARM Core
0 Reset not caused by software setting of SYSRESETREQ bit
1 Reset caused by software setting of SYSRESETREQ bit
1
LOCKUP
Core Lock-up
Table continues on the next page...
Mode Control Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
304 Freescale Semiconductor, Inc.