Information

MC_PMPROT field descriptions (continued)

Field Description

0 VLLS3 is not allowed

1 VLLS3 is allowed

AVLLS2

Allow very low leakage stop 2 mode

This write once bit allows the MCU to enter very low leakage stop 2 mode (VLLS2) provided the

appropriate control bits are set up in PMCTRL.

0 VLLS2 is not allowed

1 VLLS2 is allowed

AVLLS1

Allow very low leakage stop 1 mode

This write once bit allows the MCU to enter very low leakage stop 1 mode (VLLS1) provided the

appropriate control bits are set up in PMCTRL.

0 VLLS1 is not allowed

1 VLLS1 is allowed

13.2.4 Power Mode Control Register (MC_PMCTRL)

The PMCTRL register is used to enter the wait, low power, or low leakage modes

provided the selected power mode is allowed via appropriate setting of the protection

If the MCU is configured for a disallowed power mode or to a reserved RUNM setting,

the device remains in its current power mode. For example, if in normal run (RUNM =

00, AVLP = 0) an attempt to enter VLPR using the PMCTRL[RUNM] bits is blocked

and RUNM bits remain 00 indicating the device is still in normal run mode.

Before configuring the LPLLSM bits, the corresponding allow bit in PMPROT must be

set. Writes to LPLLSM that do not meet this criteria are ignored.

A successful write to PMPROT clears the LPLLSM bits. The state of

PMCTRL[LPLLSM] prior to clearing due to update of PMPROT indicates which power

mode was exited and should be used by initialization software for proper power mode

recovery.

NOTE

The reset value of this register depends on the reset type:

• Low-leakage wake-up (LLS exit via RESET pin or any exit

from VLLS) — bits 2-0 unaffected

• Other reset — 0x00

Mode Control Memory Map/Register Definition

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

308 Freescale Semiconductor, Inc.