Information

Section Number Title Page
36.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................864
36.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................865
36.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................866
36.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................867
36.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................867
36.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................868
36.3.10 DAC Interval n Register (PDBx_DACINTn)..............................................................................................868
36.3.11 Pulse-Out n Enable Register (PDBx_POnEN).............................................................................................869
36.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................869
36.4 Functional Description..................................................................................................................................................870
36.4.1 PDB Pre-trigger and Trigger Outputs..........................................................................................................870
36.4.2 PDB Trigger Input Source Selection...........................................................................................................872
36.4.3 DAC Interval Trigger Outputs.....................................................................................................................872
36.4.4 Pulse-Out's...................................................................................................................................................873
36.4.5 Updating the Delay Registers......................................................................................................................873
36.4.6 Interrupts......................................................................................................................................................875
36.4.7 DMA............................................................................................................................................................875
36.5 Application Information................................................................................................................................................875
36.5.1 Impact of Using the Prescaler and Multiplication Factor on Timing Resolution........................................875
Chapter 37
FlexTimer (FTM)
37.1 Introduction...................................................................................................................................................................877
37.1.1 FlexTimer Philosophy..................................................................................................................................877
37.1.2 Features........................................................................................................................................................878
37.1.3 Modes of Operation.....................................................................................................................................879
37.1.4 Block Diagram.............................................................................................................................................879
37.2 FTM Signal Descriptions..............................................................................................................................................882
37.2.1 EXTCLK — FTM External Clock...............................................................................................................882
37.2.2 CHn — FTM Channel (n) I/O Pin...............................................................................................................882
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 31