Information

The LVDSC2[LVWV] bits select one of four trip voltages:
• Highest (V
LVW4
)
• Two mid-levels (V
LVW3
and V
LVW2
)
• Lowest (V
LVW1
)
14.4 PMC Memory Map/Register Definition
The following table shows the registers related to the PMC.
See Mode Control Memory Map/Register Definition for the mode controller registers.
PMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_D000
Low Voltage Detect Status and Control 1 Register
(PMC_LVDSC1)
8 R/W 10h 14.4.1/313
4007_D001
Low Voltage Detect Status and Control 2 Register
(PMC_LVDSC2)
8 R/W 00h 14.4.2/314
4007_D002 Regulator Status and Control Register (PMC_REGSC) 8 R/W 04h 14.4.3/316
14.4.1 Low Voltage Detect Status and Control 1 Register
(PMC_LVDSC1)
This register contains status and control bits to support the low voltage detect function.
This register should be written during the reset initialization program to set the desired
controls even if the desired settings are the same as the reset settings.
While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC1 settings. To protect systems that must have LVD always
on, configure the power mode protection register (PMPROT) to disallow any very low
power or low leakage modes from being enabled.
See the device's data sheet for the exact LVD trip voltages.
NOTE
The reset value of this register depends on the reset type:
• POR -- 0x10
• Other reset -- bit 4 is set, bits 1-0 are unaffected
Chapter 14 Power Management Controller
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 313