Information

15.3 Memory map/register definition
The LLWU includes the following registers:
• Five 8-bit wakeup source enable registers
• Enable external pin input sources
• Enable internal peripheral sources
• Three 8-bit wakeup flag registers
• Indication of wakeup up source that caused exit from LLS or VLLS includes
external pin or internal module interrupt
• One 8-bit status and control register
• Digital filter enable for external pin detected and reset
• Low leakage reset pin enable
• Acknowledge bit to allow certain peripherals and pads to release their held low
leakage state
LLWU memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_C000 LLWU Pin Enable 1 Register (LLWU_PE1) 8 R/W 00h 15.3.1/323
4007_C001 LLWU Pin Enable 2 Register (LLWU_PE2) 8 R/W 00h 15.3.2/324
4007_C002 LLWU Pin Enable 3 Register (LLWU_PE3) 8 R/W 00h 15.3.3/326
4007_C003 LLWU Pin Enable 4 Register (LLWU_PE4) 8 R/W 00h 15.3.4/327
4007_C004 LLWU Module Enable Register (LLWU_ME) 8 R/W 00h 15.3.5/328
4007_C005 LLWU Flag 1 Register (LLWU_F1) 8 R/W 00h 15.3.6/329
4007_C006 LLWU Flag 2 Register (LLWU_F2) 8 R/W 00h 15.3.7/331
4007_C007 LLWU Flag 3 Register (LLWU_F3) 8 R/W 00h 15.3.8/333
4007_C008 LLWU Control and Status Register (LLWU_CS) 8 R/W 04h 15.3.9/334
15.3.1 LLWU Pin Enable 1 Register (LLWU_PE1)
LLWU_PE1 contains the bit field to enable and select the edge detect type for the
external wakeup input pins LLWU_P3-LLWU_P0.
NOTE
This register is unaffected by wakeup from low leakage modes
(exit from LLS via
RESET or any exit from VLLS).
Chapter 15 Low-leakage wake-up unit (LLWU)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 323