Information

Address: LLWU_PE1 is 4007_C000h base + 0h offset = 4007_C000h
Bit 7 6 5 4 3 2 1 0
Read
WUPE3 WUPE2 WUPE1 WUPE0
Write
Reset
0 0 0 0 0 0 0 0
LLWU_PE1 field descriptions
Field Description
7–6
WUPE3
Wakeup Pin Enable for LLWU_P3
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
5–4
WUPE2
Wakeup Pin Enable for LLWU_P2
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
3–2
WUPE1
Wakeup Pin Enable for LLWU_P1
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
1–0
WUPE0
Wakeup Pin Enable for LLWU_P0
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
15.3.2 LLWU Pin Enable 2 Register (LLWU_PE2)
LLWU_PE2 contains the bit field to enable and select the edge detect type for the
external wakeup input pins LLWU_P7-LLWU_P4.
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
324 Freescale Semiconductor, Inc.