Information

15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3)
LLWU_PE3 contains the bit field to enable and select the edge detect type for the
external wakeup input pins LLWU_P11-LLWU_P8.
NOTE
This register is unaffected by wakeup from low leakage modes
(exit from LLS via RESET or any exit from VLLS).
Address: LLWU_PE3 is 4007_C000h base + 2h offset = 4007_C002h
Bit 7 6 5 4 3 2 1 0
Read
WUPE11 WUPE10 WUPE9 WUPE8
Write
Reset
0 0 0 0 0 0 0 0
LLWU_PE3 field descriptions
Field Description
7–6
WUPE11
Wakeup Pin Enable for LLWU_P11
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
5–4
WUPE10
Wakeup Pin Enable for LLWU_P10
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
3–2
WUPE9
Wakeup Pin Enable for LLWU_P9
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
1–0
WUPE8
Wakeup Pin Enable for LLWU_P8
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
326 Freescale Semiconductor, Inc.