Information

MCM_ETBCC field descriptions (continued)
Field Description
If debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit
clears the debug halt request.
0 No effect
1 Clears pending debug halt, NMI, or IRQ interrupt requests
2–1
RSPT
Response type
00 No response when the ETB count expires
01 Generate a normal interrupt when the ETB count expires
10 Generate an NMI when the ETB count expires
11 Generate a debug halt when the ETB count expires
0
CNTEN
Counter enable
Enables the ETB counter.
0 ETB counter disabled
1 ETB counter enabled
16.2.6 ETB reload register (MCM_ETBRL)
Address: MCM_ETBRL is E008_0000h base + 18h offset = E008_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RELOAD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_ETBRL field descriptions
Field Description
31–11
Reserved
This read-only field is reserved and always has the value zero.
10–0
RELOAD
Byte count reload value
Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4 value to this field results in an
bus error
Memory Map/Register Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
344 Freescale Semiconductor, Inc.