Information

Slave Port n Internal
Region
Descriptor 0
Region
Descriptor 1
Region
Descriptor x
Access
Evaluation
Macro
Access
Evaluation
Macro
Access
Evaluation
Macro
Mux
Address Phase Signals Peripheral Bus
MPU_EARn MPU_EDRn
Figure 18-1. MPU Block Diagram
18.2.2 Features
The MPU implements a two-dimensional hardware array of memory region descriptors
and the crossbar slave ports to continuously monitor the legality of every memory
reference generated by each bus master in the system. The feature set includes:
• 12 program-visible 128-bit region descriptors, accessible by four 32-bit words each
• Each region descriptor defines a modulo-32 byte space, aligned anywhere in
memory
• Region sizes can vary from 32 bytes to 4 Gbytes
• Two access control permissions defined in a single descriptor word
• Masters 0–3: read, write, and execute attributes for supervisor and user
accesses
• Masters 4–7: read and write attributes
• Hardware-assisted maintenance of the descriptor valid bit minimizes coherency
issues
Overview
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
362 Freescale Semiconductor, Inc.