Information

18.3.5 Region Descriptor n, Word 1 (MPU_RGD_WORD1)
The second word of the region descriptor defines the 31-modulo-32 byte end address of
the memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
Addresses: 4000_D000h base + 404h offset + (16d × n), where n = 0d to 11d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENDADDR
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
MPU_RGDn_WORD1 field descriptions
Field Description
31–5
ENDADDR
End address
Defines the most significant bits of the 31-modulo-32 byte end address of the memory region.
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.
4–0
Reserved
This field is reserved.
18.3.6 Region Descriptor n, Word 2 (MPU_RGD_WORD2)
The third word of the region descriptor defines the access control rights of the memory
region. The access control privileges depend on two broad classifications of bus masters:
• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and
supervisor mode accesses.
• Bus masters 4–7 are limited to separate read and write permissions.
For the privilege rights of bus masters 0–3, there are three flags associated with this
function:
• Read (r) refers to accessing the referenced memory address using an operand (data)
fetch
• Write (w) refers to updating the referenced memory address using a store (data)
instruction
• Execute (x) refers to reading the referenced memory address using an instruction
fetch
Chapter 18 Memory Protection Unit (MPU)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 371