Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 144 (13x13) 32-Bit 100 MHz I/O number 104

Section Number Title Page

42.3.7 Rx 15 Mask Register (CANx_RX15MASK)...............................................................................................1099

42.3.8 Error Counter (CANx_ECR)........................................................................................................................1100

42.3.9 Error and Status 1 Register (CANx_ESR1).................................................................................................1101

42.3.10 Interrupt Masks 2 Register (CANx_IMASK2)............................................................................................1105

42.3.11 Interrupt Masks 1 Register (CANx_IMASK1)............................................................................................1106

42.3.12 Interrupt Flags 2 Register (CANx_IFLAG2)...............................................................................................1106

42.3.13 Interrupt Flags 1 Register (CANx_IFLAG1)...............................................................................................1107

42.3.14 Control 2 Register (CANx_CTRL2)............................................................................................................1110

42.3.15 Error and Status 2 Register (CANx_ESR2).................................................................................................1113

42.3.16 CRC Register (CANx_CRCR).....................................................................................................................1114

42.3.17 Rx FIFO Global Mask Register (CANx_RXFGMASK).............................................................................1115

42.3.18 Rx FIFO Information Register (CANx_RXFIR).........................................................................................1116

42.3.19 Rx Individual Mask Registers (CANx_RXIMRn).......................................................................................1117

42.3.56 Message Buffer Structure.............................................................................................................................1118

42.3.57 Rx FIFO Structure........................................................................................................................................1124

42.4 Functional Description..................................................................................................................................................1127

42.4.1 Transmit Process..........................................................................................................................................1127

42.4.2 Arbitration process.......................................................................................................................................1128

42.4.3 Receive Process............................................................................................................................................1132

42.4.4 Matching Process.........................................................................................................................................1134

42.4.5 Move Process...............................................................................................................................................1138

42.4.6 Data Coherence............................................................................................................................................1140

42.4.7 Rx FIFO.......................................................................................................................................................1144

42.4.8 CAN Protocol Related Features...................................................................................................................1145

42.4.9 Modes of Operation Details.........................................................................................................................1152

42.4.10 Interrupts......................................................................................................................................................1156

42.4.11 Bus Interface................................................................................................................................................1157

42.5 Initialization/Application Information..........................................................................................................................1158

42.5.1 FlexCAN Initialization Sequence................................................................................................................1158

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

38 Freescale Semiconductor, Inc.