Information

Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The peripheral bridge (AIPS-Lite) converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
The peripheral bridge supports up to 128 peripherals. The peripheral bridge occupies a 64
MB portion of the address space. The bridge includes separate clock enable inputs for
each of the slots to accommodate slower peripherals.
19.1.1 Features
Key features of the peripheral bridge are:
• Supports up to 128 peripherals
• Supports 8-, 16-, and 32-bit width peripheral slots
• Each independently configurable peripheral includes a clock enable, which allows
peripherals to operate at any speed less than the system clock rate.
• Programming model provides memory protection functionality
19.1.2 General operation
The peripherals connected to the peripheral bridge are modules that contain readable/
writable control and status registers. The system masters read and write these registers
through the peripheral bridge. The peripheral bridge generates module enables, the
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 383