Information

NOTE
At reset, the default value loaded into the MPROT[7-0] fields is
device-specific. See the Chip Configuration details for the value
on your particular device.
Accesses to registers or register fields which correspond to master or peripheral locations
which are not implemented return zeros on reads, and are ignored on writes.
Each master is assigned depending on its connection to the crossbar switch master ports.
See your device-specific Chip Configuration details for information about the master
assignments to these registers.
Addresses: AIPS0_MPRA is 4000_0000h base + 0h offset = 4000_0000h
AIPS1_MPRA is 4008_0000h base + 0h offset = 4008_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MTR0
MTW0
MPL0
0
MTR1
MTW1
MPL1
0
MTR2
MTW2
MPL2
0
MTR3
MTW3
MPL3
0
MTR4
MTW4
MPL4
0
MTR5
MTW5
MPL5
0 0
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
AIPSx_MPRA field descriptions
Field Description
31
Reserved
This read-only field is reserved and always has the value zero.
30
MTR0
Master trusted for read
Determines whether the master is trusted for read accesses.
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
29
MTW0
Master trusted for writes
Determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
28
MPL0
Master privilege level
Specifies how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
27
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
386 Freescale Semiconductor, Inc.