Information

AIPSx_MPRA field descriptions (continued)
Field Description
3–0
Reserved
This read-only field is reserved and always has the value zero.
19.2.2 Peripheral Access Control Register (AIPSx_PACRn)
Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels
supported by the given module. Eight PACR fields are grouped together to form a 32-bit
PACR[A:P] register:
• PACRA-P define the access levels for the 128 peripherals
The peripheral assignments to each PACR register is defined by the memory map slot
that the peripherals are assigned.See the device's Memory Map details for the
assignments for your particular device.
NOTE
The reset value of the PACRA-D registers is 0x4444_4444.
The following table shows the top-level structure of the PACR registers.
Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0]
0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15
0x28 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23
0x2C PACRD PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31
0x30 Reserved
0x34 Reserved
0x38 Reserved
0x3C Reserved
0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 PACR39
0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55
0x4C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63
0x50 PACRI PACR64 PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71
0x54 PACRJ PACR72 PACR73 PACR74 PACR75 PACR76 PACR77 PACR78 PACR79
0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 PACR85 PACR86 PACR87
0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 PACR95
Table continues on the next page...
Chapter 19 Peripheral Bridge (AIPS-Lite)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 389