Information

Section Number Title Page
Chapter 43
SPI (DSPI)
43.1 Introduction...................................................................................................................................................................1161
43.1.1 Block Diagram.............................................................................................................................................1161
43.1.2 Features........................................................................................................................................................1162
43.1.3 DSPI Configurations....................................................................................................................................1163
43.1.4 Modes of Operation.....................................................................................................................................1164
43.2 DSPI Signal Descriptions.............................................................................................................................................1166
43.2.1 PCS0/SS — Peripheral Chip Select/Slave Select........................................................................................1166
43.2.2 PCS1 - PCS3 — Peripheral Chip Selects 1 - 3............................................................................................1166
43.2.3 PCS4 — Peripheral Chip Select 4................................................................................................................1167
43.2.4 PCS5/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe.....................................................1167
43.2.5 SIN — Serial Input......................................................................................................................................1167
43.2.6 SOUT — Serial Output................................................................................................................................1167
43.2.7 SCK — Serial Clock....................................................................................................................................1167
43.3 Memory Map/Register Definition.................................................................................................................................1168
43.3.1 DSPI Module Configuration Register (SPIx_MCR)....................................................................................1171
43.3.2 DSPI Transfer Count Register (SPIx_TCR)................................................................................................1174
43.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)......................................1174
43.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)..........................1179
43.3.5 DSPI Status Register (SPIx_SR)..................................................................................................................1180
43.3.6 DSPI DMA/Interrupt Request Select and Enable Register (SPIx_RSER)..................................................1183
43.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)...............................................................1185
43.3.8 DSPI PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)..................................................1187
43.3.9 DSPI POP RX FIFO Register (SPIx_POPR)...............................................................................................1187
43.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn)...........................................................................................1188
43.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)............................................................................................1188
43.4 Functional Description..................................................................................................................................................1189
43.4.1 Start and Stop of DSPI Transfers.................................................................................................................1190
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 39