Information

Section Number Title Page
43.4.2 Serial Peripheral Interface (SPI) Configuration...........................................................................................1190
43.4.3 DSPI Baud Rate and Clock Delay Generation.............................................................................................1194
43.4.4 Transfer Formats..........................................................................................................................................1198
43.4.5 Continuous Serial Communications Clock..................................................................................................1203
43.4.6 Slave Mode Operation Constraints..............................................................................................................1204
43.4.7 Interrupts/DMA Requests............................................................................................................................1205
43.4.8 Power Saving Features.................................................................................................................................1207
43.5 Initialization/Application Information..........................................................................................................................1208
43.5.1 How to Manage DSPI Queues.....................................................................................................................1208
43.5.2 Switching Master and Slave Mode..............................................................................................................1209
43.5.3 Baud Rate Settings.......................................................................................................................................1210
43.5.4 Delay Settings..............................................................................................................................................1210
43.5.5 Calculation of FIFO Pointer Addresses.......................................................................................................1211
Chapter 44
Inter-Integrated Circuit (I2C)
44.1 Introduction...................................................................................................................................................................1215
44.1.1 Features........................................................................................................................................................1215
44.1.2 Modes of Operation.....................................................................................................................................1216
44.1.3 Block Diagram.............................................................................................................................................1216
44.2 I2C Signal Descriptions................................................................................................................................................1217
44.3 Memory Map and Register Descriptions......................................................................................................................1217
44.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................1219
44.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................1219
44.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................1220
44.3.4 I2C Status Register (I2Cx_S).......................................................................................................................1222
44.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................1224
44.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................1225
44.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................1226
44.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1226
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
40 Freescale Semiconductor, Inc.