Information

DMAMUX memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_1000 Channel Configuration Register (DMAMUX_CHCFG0) 8 R/W 00h 20.3.1/404
4002_1001 Channel Configuration Register (DMAMUX_CHCFG1) 8 R/W 00h 20.3.1/404
4002_1002 Channel Configuration Register (DMAMUX_CHCFG2) 8 R/W 00h 20.3.1/404
4002_1003 Channel Configuration Register (DMAMUX_CHCFG3) 8 R/W 00h 20.3.1/404
4002_1004 Channel Configuration Register (DMAMUX_CHCFG4) 8 R/W 00h 20.3.1/404
4002_1005 Channel Configuration Register (DMAMUX_CHCFG5) 8 R/W 00h 20.3.1/404
4002_1006 Channel Configuration Register (DMAMUX_CHCFG6) 8 R/W 00h 20.3.1/404
4002_1007 Channel Configuration Register (DMAMUX_CHCFG7) 8 R/W 00h 20.3.1/404
4002_1008 Channel Configuration Register (DMAMUX_CHCFG8) 8 R/W 00h 20.3.1/404
4002_1009 Channel Configuration Register (DMAMUX_CHCFG9) 8 R/W 00h 20.3.1/404
4002_100A Channel Configuration Register (DMAMUX_CHCFG10) 8 R/W 00h 20.3.1/404
4002_100B Channel Configuration Register (DMAMUX_CHCFG11) 8 R/W 00h 20.3.1/404
4002_100C Channel Configuration Register (DMAMUX_CHCFG12) 8 R/W 00h 20.3.1/404
4002_100D Channel Configuration Register (DMAMUX_CHCFG13) 8 R/W 00h 20.3.1/404
4002_100E Channel Configuration Register (DMAMUX_CHCFG14) 8 R/W 00h 20.3.1/404
4002_100F Channel Configuration Register (DMAMUX_CHCFG15) 8 R/W 00h 20.3.1/404
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same Source value
will result in unpredictable behavior.
NOTE
Before changing the trigger or source settings a DMA channel
must be disabled via the CHCFGn[ENBL] bit.
Addresses: 4002_1000h base + 0h offset + (1d × n), where n = 0d to 15d
Bit 7 6 5 4 3 2 1 0
Read
ENBL TRIG SOURCE
Write
Reset
0 0 0 0 0 0 0 0
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
404 Freescale Semiconductor, Inc.