Information

Section Number Title Page
44.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1227
44.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1228
44.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1229
44.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1229
44.4 Functional Description..................................................................................................................................................1230
44.4.1 I2C Protocol.................................................................................................................................................1230
44.4.2 10-bit Address..............................................................................................................................................1235
44.4.3 Address Matching........................................................................................................................................1236
44.4.4 System Management Bus Specification.......................................................................................................1237
44.4.5 Resets...........................................................................................................................................................1240
44.4.6 Interrupts......................................................................................................................................................1240
44.4.7 Programmable Input Glitch Filter................................................................................................................1242
44.4.8 Address Matching Wakeup..........................................................................................................................1242
44.4.9 DMA Support...............................................................................................................................................1243
44.5 Initialization/Application Information..........................................................................................................................1243
Chapter 45
Universal Asynchronous Receiver/Transmitter (UART)
45.1 Introduction...................................................................................................................................................................1247
45.1.1 Features........................................................................................................................................................1247
45.1.2 Modes of operation......................................................................................................................................1249
45.2 UART signal descriptions.............................................................................................................................................1250
45.2.1 Detailed signal descriptions.........................................................................................................................1250
45.3 Memory map and registers............................................................................................................................................1251
45.3.1 UART Baud Rate Registers:High (UARTx_BDH).....................................................................................1261
45.3.2 UART Baud Rate Registers: Low (UARTx_BDL).....................................................................................1262
45.3.3 UART Control Register 1 (UARTx_C1).....................................................................................................1263
45.3.4 UART Control Register 2 (UARTx_C2).....................................................................................................1265
45.3.5 UART Status Register 1 (UARTx_S1)........................................................................................................1267
45.3.6 UART Status Register 2 (UARTx_S2)........................................................................................................1270
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 41