Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9054
TCD Signed Destination Address Offset
(DMA_TCD2_DOFF)
16 R/W Undefined
21.3.25/
461
4000_9056
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD2_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
461
4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined
21.3.27/
462
4000_9058
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD2_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined
21.3.29/
464
4000_905E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD2_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
466
4000_905E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD2_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
467
4000_9060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined
21.3.17/
455
4000_9064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined
21.3.18/
456
4000_9066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined
21.3.19/
456
4000_9068
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD3_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
457
4000_9068
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
458
4000_9068
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD3_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
459
4000_906C
TCD Last Source Address Adjustment
(DMA_TCD3_SLAST)
32 R/W Undefined
21.3.23/
460
4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined
21.3.24/
460
4000_9074
TCD Signed Destination Address Offset
(DMA_TCD3_DOFF)
16 R/W Undefined
21.3.25/
461
4000_9076
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD3_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
461
4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined
21.3.27/
462
4000_9078
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD3_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined
21.3.29/
464
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
422 Freescale Semiconductor, Inc.