Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined
21.3.19/
456
4000_90A8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD5_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
457
4000_90A8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
458
4000_90A8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD5_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
459
4000_90AC
TCD Last Source Address Adjustment
(DMA_TCD5_SLAST)
32 R/W Undefined
21.3.23/
460
4000_90B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined
21.3.24/
460
4000_90B4
TCD Signed Destination Address Offset
(DMA_TCD5_DOFF)
16 R/W Undefined
21.3.25/
461
4000_90B6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD5_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
461
4000_90B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined
21.3.27/
462
4000_90B8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD5_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_90BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined
21.3.29/
464
4000_90BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD5_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
466
4000_90BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD5_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
467
4000_90C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined
21.3.17/
455
4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined
21.3.18/
456
4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined
21.3.19/
456
4000_90C8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD6_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
457
4000_90C8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD6_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
458
4000_90C8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD6_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
459
4000_90CC
TCD Last Source Address Adjustment
(DMA_TCD6_SLAST)
32 R/W Undefined
21.3.23/
460
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
424 Freescale Semiconductor, Inc.