Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) 16 R/W Undefined
21.3.18/
456
4000_9126 TCD Transfer Attributes (DMA_TCD9_ATTR) 16 R/W Undefined
21.3.19/
456
4000_9128
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD9_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
457
4000_9128
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD9_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
458
4000_9128
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD9_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
459
4000_912C
TCD Last Source Address Adjustment
(DMA_TCD9_SLAST)
32 R/W Undefined
21.3.23/
460
4000_9130 TCD Destination Address (DMA_TCD9_DADDR) 32 R/W Undefined
21.3.24/
460
4000_9134
TCD Signed Destination Address Offset
(DMA_TCD9_DOFF)
16 R/W Undefined
21.3.25/
461
4000_9136
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD9_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
461
4000_9136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined
21.3.27/
462
4000_9138
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD9_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_913C TCD Control and Status (DMA_TCD9_CSR) 16 R/W Undefined
21.3.29/
464
4000_913E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD9_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
466
4000_913E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD9_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
467
4000_9140 TCD Source Address (DMA_TCD10_SADDR) 32 R/W Undefined
21.3.17/
455
4000_9144 TCD Signed Source Address Offset (DMA_TCD10_SOFF) 16 R/W Undefined
21.3.18/
456
4000_9146 TCD Transfer Attributes (DMA_TCD10_ATTR) 16 R/W Undefined
21.3.19/
456
4000_9148
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD10_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
457
4000_9148
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD10_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
458
4000_9148
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD10_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
459
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 427