Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9178
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD11_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined
21.3.29/
464
4000_917E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD11_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
466
4000_917E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD11_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
467
4000_9180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined
21.3.17/
455
4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined
21.3.18/
456
4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined
21.3.19/
456
4000_9188
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD12_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
457
4000_9188
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD12_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
458
4000_9188
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD12_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
459
4000_918C
TCD Last Source Address Adjustment
(DMA_TCD12_SLAST)
32 R/W Undefined
21.3.23/
460
4000_9190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined
21.3.24/
460
4000_9194
TCD Signed Destination Address Offset
(DMA_TCD12_DOFF)
16 R/W Undefined
21.3.25/
461
4000_9196
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD12_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
461
4000_9196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined
21.3.27/
462
4000_9198
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD12_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_919C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined
21.3.29/
464
4000_919E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD12_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
466
4000_919E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD12_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
467
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 429