Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_91F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined
21.3.27/
462
4000_91F8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD15_DLASTSGA)
32 R/W Undefined
21.3.28/
463
4000_91FC TCD Control and Status (DMA_TCD15_CSR) 16 R/W Undefined
21.3.29/
464
4000_91FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD15_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
466
4000_91FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD15_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
467
21.3.1 Control Register (DMA_CR)
The CR defines the basic operating configuration of the DMA.
Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For
fixed-priority arbitration, the highest priority channel requesting service is selected to
execute. The channel priority registers assign the priorities; see the DCHPRIn registers.
For round-robin arbitration, the channel priorities are ignored and channels are cycled
through without regard to priority.
NOTE
For proper operation, writes to the CR register must be
performed only when the DMA channels are inactive; that is,
when TCDn_CSR[ACTIVE] bits are cleared.
Address: DMA_CR is 4000_8000h base + 0h offset = 4000_8000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CX
ECX
0
EMLM
CLM
HALT
HOE
0
ERCA
EDBG
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CR field descriptions
Field Description
31–18
Reserved
This read-only field is reserved and always has the value zero.
17
CX
Cancel Transfer
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
432 Freescale Semiconductor, Inc.