Information

Section Number Title Page
46.4 Memory map and register definition.............................................................................................................................1346
46.4.1 DMA System Address Register (SDHC_DSADDR)..................................................................................1347
46.4.2 Block Attributes Register (SDHC_BLKATTR)..........................................................................................1348
46.4.3 Command Argument Register (SDHC_CMDARG)....................................................................................1349
46.4.4 Transfer Type Register (SDHC_XFERTYP)..............................................................................................1350
46.4.5 Command Response 0 (SDHC_CMDRSP0)...............................................................................................1354
46.4.6 Command Response 1 (SDHC_CMDRSP1)...............................................................................................1355
46.4.7 Command Response 2 (SDHC_CMDRSP2)...............................................................................................1355
46.4.8 Command Response 3 (SDHC_CMDRSP3)...............................................................................................1355
46.4.9 Buffer Data Port Register (SDHC_DATPORT)..........................................................................................1357
46.4.10 Present State Register (SDHC_PRSSTAT).................................................................................................1357
46.4.11 Protocol Control Register (SDHC_PROCTL).............................................................................................1362
46.4.12 System Control Register (SDHC_SYSCTL)...............................................................................................1366
46.4.13 Interrupt Status Register (SDHC_IRQSTAT).............................................................................................1369
46.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN)............................................................................1375
46.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN)...............................................................................1378
46.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)...........................................................................1380
46.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)....................................................................................1383
46.4.18 Watermark Level Register (SDHC_WML).................................................................................................1385
46.4.19 Force Event Register (SDHC_FEVT)..........................................................................................................1385
46.4.20 ADMA Error Status Register (SDHC_ADMAES)......................................................................................1388
46.4.21 ADMA System Address Register (SDHC_ADSADDR).............................................................................1390
46.4.22 Vendor Specific Register (SDHC_VENDOR)............................................................................................1390
46.4.23 MMC Boot Register (SDHC_MMCBOOT)................................................................................................1392
46.4.24 Host Controller Version (SDHC_HOSTVER)............................................................................................1393
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
44 Freescale Semiconductor, Inc.