Information

DMA_INT field descriptions (continued)
Field Description
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
10
INT10
Interrupt Request 10
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
9
INT9
Interrupt Request 9
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
8
INT8
Interrupt Request 8
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
7
INT7
Interrupt Request 7
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
6
INT6
Interrupt Request 6
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
5
INT5
Interrupt Request 5
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
4
INT4
Interrupt Request 4
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
3
INT3
Interrupt Request 3
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
2
INT2
Interrupt Request 2
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
1
INT1
Interrupt Request 1
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
0
INT0
Interrupt Request 0
0 The interrupt request for corresponding channel is cleared
1 The interrupt request for corresponding channel is active
Chapter 21 Direct Memory Access Controller (eDMA)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 449